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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2002 - 2004, zarlink semiconductor inc. all rights reserved. features ? single chip synthesised downconverter forming a complete double conversion tuner when combined with the sl2100 or sl2101 ? compatible with digital and analogue system requirements ? ctb contribution < -64 dbc, cxm contribution < -62 dbc and spectral spread < -64 dbc ? if amplifier optimized to interface with standard saw filters ? extremely low phase noise balanced local oscillator, with very low fundamental and harmonic radiation ? pll frequency synthesizer designed for high comparison frequencies and low phase noise ? available in 28 pin ssop and mlp packages applications ? double conversion tuners ? digital terrestrial tuners ? cable modems ? cable telephony ?matv description the zl10100 is a fully integrated single chip mixer oscillator with on-board low phase noise i2c bus controlled pll frequency synthesizer. it is intended primarily as the down converter for application in double conversion tuners and is compatible with hiif frequencies between 1 and 1.3 ghz and all standard tuner if output frequencies. the device contains all elements necessary, with the exception of local oscillat or tuning network, loop filter and crystal reference to fabricate a complete synthesized block converter with if amplifier, compatible with digital and analogue requirements. august 2004 ordering information zl10100/dde ssop tubes zl10100/ddf ssop tape & reel, zl10100/dde1 ssop* tubes zl10100/ddf1 ssop* tape & reel zl10100/ldg1 mlp* trays zl10100/ldf1 mlp* tape & reel * pb free all codes baked an drypacked -40 c to +85 c zl10100 single chip synthesized downconverter with if amplifier data sheet figure 1 - zl10100 functional block diagram rf input rf inputb if output if outputb vco lo lob charge pump 15 bit programmable divider pump drive fpd/ 2 i2c bus interface sda scl add reference divider ref osc port p0 fpd/2 fcomp xtal xtalcap
zl10100 data sheet 2 zarlink semiconductor inc. pin description figure 2 - pin description ssop package figure 3 - pin description mlp package ifoutputb vee vccrf vee rfinputb rfinput vee vee vccd vee scl sda xtal xtal cap ifoutput vee vccif vee vcclo lo lob vcclo vee add vee port p0 drive pump 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 pin 1 ident nc vcclo lo lob vcclo add nc vee to pad under package sda xtal xtal cap vee pump drive port p0 nc rfinputb nc rfinput nc vccd scl vccrf vee ifoutputb nc ifoutput vee vccif 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
zl10100 data sheet 3 zarlink semiconductor inc. quick reference data all data applies with the following conditions unless otherwise stated; a) output load of 150 ? , differential b) input spectrum of 5 channels c entred on 1220 mhz, each carrier @ 77 db v characteristic units rf input operating range 1-1.3 ghz if output operating range 30-60 mhz input noise figure, ssb 9 db conversion gain, diff to diff 24 db ctb < ? 66 dbc cxm < ? 63 dbc spectral spread < ? 70 dbc local oscillator phase noise ssb @ 10 khz offset ssb @ 100 khz offset c -93 c-115 dbc/hz dbc/hz local oscillator phase noise floor -136 dbc/hz if output impedance, differential 150 ? pll phase noise at phase detector, 1 mhz comparison frequency -152 dbc/hz
zl10100 data sheet 4 zarlink semiconductor inc. 1.0 functional description the zl10100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board i2c bus controlled pll frequency synthesizer, optimized for application as the down converter in double conversion tuner systems. it also has application in any system where a wide dynamic r ange broadband synthesized frequency converter is required. the zl10100 is a single chip solution containing all necessa ry active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. the pin assignment is contained in the block diagram in figure 1 and the pin description in figure 2. 1.1 converter section in normal application the hiif input is interfaced thr ough appropriate impedance matchi ng to the device input. the rf input preamplifier of the device is designed for low noise figure, within the operating region of 1 to 1.3 ghz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. the preamplifier also provides gain to the mixer section and back isolation from the local oscillato r section. the typical rf input im pedance and matching net work for matching to a 1220 mhz hiif filter, type b1603 are contained in figures 3 and 4. the output of the preamplifier is fed to the mixer section which is optimized for low radiation application. in this stage the rf signal is mixe d with the local oscillator fr equency, which is generated by the on-board oscillator. the oscillator block uses an external tuneable network and is optimized for low phase noise. the typical application is shown in figure 6, and the phase noise performance in figure 7. this block interfaces direct with the internal pll to allow for frequency synthesis of the local oscillator. the output of the mixer is internally coupled to a differen tial if amplifier, which prov ides further gain and provides for a 150 ? , differential output impedanc e and drive capability. the if amplif ier allows for if frequencies between 30 and 60 mhz. the typical if output impedance is contained in figure 8. the typical key performance data at 5 v vcc and 25 deg c ambient are shown in the quick reference data section on page 2. 1.2 local oscillator to maximize the local oscillator phas e noise performance, the application circuit as in figure 5 must be carefully adhered to including the component type and manufact ure where applicable, strip line dimension and board material. any deviation from these pa rameters may adversely af fect phase noise characteri stics and so will require re-optimization. 1.3 pll frequency synthesizer the pll frequency synthesizer section co ntains all the elements necessary, with the exception of a reference frequency source and loop filter to c ontrol the oscillator, so forming a co mplete pll frequency synthesized source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop wi th good phase noise performance. the lo signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier interfaces direct with the 15-bit fully programmable divider. the programmable divider is of mn+a archit ecture, where the dual modulus prescale r is 16/17, the a counter is 4-bits, and the m counter is 11 bits. the output of the programm able divider is fed to the phase comparat or where it is compared in both phase and frequency domain with the comparison frequency. this fr equency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the referenc e frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in table 1.
zl10100 data sheet 5 zarlink semiconductor inc. the typical application for the crystal oscillator is co ntained in figure 9 which also demonstrates how a 4 mhz reference signal can be coupled out to a further pll fr equency synthesizer, such as the upconverter section in a double conversion tuner. the output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integr ates the current pulses into the varactor line voltage, used for controlling the oscillator. the programmable divider output fpd divided by two an d the reference divider output fcomp can be switched to port p0 by programming the device into test mode. the test modes are described in table 2. 2.0 programming the zl10100 is controlled by an i2c data bus and is compatible with both standard and fast mode formats. data and clock are fed in on the sda and scl lines respectively as defined by i2c bus format. the device can either accept data (write mo de), or send data (read mode). the lsb of t he address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. tables 3, 4 and 5 illustra te the format of the data. the device can be programmed to respond to several addresses, which en ables the use of more than one device in an i2c bus system. table 5 shows how the address is selected by applying a voltage to the 'add' input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge pe riod, and during following acknowledge periods after further data bytes are received . when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte ackn owledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the de vice generates an internal stop condition, which inhibits further reading. 2.1 write mode with reference to table 5, bytes 2 and 3 contain frequency information bits 214-20 inclusive. byte 4 controls the synthesizer reference divider ratio, see table 1 and the charge pump setting , see table 6. byte 5 controls the test modes, see table 2 and the output port p0. after reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0 ' indicating byte 2, and a logic '1' indicating byte 4. having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data by tes can be entered, where byte interpretation follows the same procedure, without re-addres sing the device. this procedure continues until a stop condition is received. the stop condition can be generated after an y data byte, if however it occurs during a byte transmission, the previous byte data is retained. to fa cilitate smooth fine tuning, th e frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. 2.2 read mode when the device is in read mode, the status byte r ead from the device takes the form shown in table 4. bit 1 (por) is the power-on reset indicator, and this is set to a logic '1' if the vcc supply to the device has dropped below 3 v (at 25c), e.g., when the device is initially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high th is indicates that the programmed information may have been corrupted and the device reset to the power up condition. bit 2 (fl) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked.
zl10100 data sheet 6 zarlink semiconductor inc. figure 4 - typical rf input impedance figure 5 - rf input impedance matching network to b1603 hiif filter programmable features synthesizer programmable divi der function as described above. reference programmable divider function as described above. charge pump current the charge pump current can be programmed by bits c1 and c0 within data byte 4, as defined in table 6. test mode the test modes are defined by bits t2-t0 as described in table 2. general purpose ports, p0 the general purpose port can be programmed by bits p0; logic ?1? = on logic ?0? = off (high impedance) ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 300.000 000 mhz b1 4.7v cor avg 16 smo prm z 0 50 26 jun 2002 14:18:23 1 2 3 4 1_: 33.309 -74.777 2.1284 pf 1 000.000 000 mhz 2_: 29.262 -66.289 1.1 ghz 3_: 24.57 -58.744 1.22 ghz 4_: 22.332 -54.303 1.3 ghz 5 6 6 5 8.2 nh 2.7 pf 2.7 pf zl10100 b1603
zl10100 data sheet 7 zarlink semiconductor inc. figure 6 - oscillator application figure 7 - typical phase noise performance with application as in figure 6 1 k ? varactor line bb555 4.3 nh 23 22 2pf 1 k ? varactor line bb555 4.3 nh 23 22 2pf 1 k ? -110 -105 -100 -95 -90 -85 -80 1010 1060 1110 1160 1210 lo frequency (mhz) phase noise (@ 10khz offset), dbc
zl10100 data sheet 8 zarlink semiconductor inc. figure 8 - typical if output impedance single-ended ch1 s 11 1 u fs start 30.000 000 mhz stop 60.000 000 mhz b1 pin1 4.7v cor avg 16 smo prm z 0 75 25 jun 2002 06:58:03 1 2 3 4 1_: 76.695 -5.6172 944.45 pf 30.000 000 mhz 2_: 75.914 -7.2539 44 mhz 3_: 75.391 -7.9023 50 mhz 4_: 74.152 -9.207 60 mhz
zl10100 data sheet 9 zarlink semiconductor inc. table 1 - reference division ratios figure 9 - crystal oscillator application r4 r3 r2 r1 r0 ratio 00000 2 00001 4 00010 8 00011 16 00100 32 00101 64 00110 128 00111 256 0 1 0 0 0 illegal state 01001 5 01010 10 01011 20 01100 40 01101 80 01110 160 01111 320 1 0 0 0 0 illegal state 10001 6 10010 12 10011 24 10100 48 10101 96 10110 192 10111 384 1 1 0 0 0 illegal state 11001 7 11010 14 11011 28 11100 56 11101 112 11110 224 11111 448 reference 47 pf 10 pf xtalcap xtal 47 pf 4 mhz frequency output
zl10100 data sheet 10 zarlink semiconductor inc. table 2 - test modes * clocks need to be pres ent on crystal and loca l oscillator to enable charge pump test modes and to toggle status byte bit fl table 3 - write data format (msb is transmitted first) table 4 - read data format (msb is transmitted first) a : acknowledge bit ma1,ma0 : variable address bits (see table 5) 2 14 -2 0 : programmable division ratio control bits c1-c0 : charge pump current select (see table 6) r4-r0 : reference division ratio select (see table 1) t2-t0 : test mode control bits (see table 2) p0 : p0 port output state por : power on reset indicator fl : phase lock flag x : 'don't care' table 5 - address selection # programmed by connecting a 30 k ? resistor between pin and vcc t2 t1 t0 test mode description 0 0 0 normal operation 0 0 1 charge pump sink* status byte fl set to logic ?0? 0 1 0 charge pump source* status byte fl set to logic ?0? 0 1 1 charge pump disabled* status byte fl set to logic ?1? 1 0 0 normal operation and port p0 = fpd/2 1 0 0 charge pump sink* status byte fl set to logic ?0? port p0 = fcomp 1 1 0 charge pump source* status byte fl set to logic ?0? port p0 = fcomp 1 1 1 charge pump disabled* status byte fl set to logic ?1? port p0 = fcomp msb lsb address 1 1 0 0 0 ma1 ma0 0 a byte 1 programmable divider 0 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 c1 c0 r4 r3 r2 r1 r0 a byte 4 control data t2 t1 t0 x x x 0 p0 a byte 5 msb lsb address 1 1 0 0 0 ma1 ma0 1 a byte 1 status byte por fl 0 0 0 0 0 0 a byte 2 ma1 ma0 address input voltage level 0 0 1 1 0 1 0 1 0-0.1 vcc open circuit 0.4vcc - 0.6 vcc # 0.9 vcc - vcc
zl10100 data sheet 11 zarlink semiconductor inc. table 6 - charge pump current c1 c0 current in a min. typ. max. 0 0 1 1 0 1 0 1 98 210 450 975 130 280 600 1300 162 350 750 1625 electrical characteristics - test conditions (unless otherwise stated) t amb = -40 c to 85 c, vee = 0 v, vcc = 5 v5%. input frequency 1220 mhz. if output frequency 44 mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature a nd supply voltage unless otherwise stated. characteristic pin min. typ. max. units conditions supply current 120 160 ma input frequency range 1 1.3 ghz composite peak input signal 86 db v operating condition only. input impedance see figure 4. input noise figure 9 11 db tamb = 27 c conversion gain 20 23 26 db di fferential to differential voltage gain to differential 150 ? load. gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range. through gain -30 db ctb -64 dbc see note 4. cxm -62 dbc see note 4. lo operating range 0.9 1.6 ghz maximum tuning range determined by application, see note (3), guaranteed by design. lo phase noise, ssb @ 10 khz offset @ 100 khz offset -94 -116 -90 -110 dbc/hz dbc/hz see figure 7. application as in figure 6. lo phase noise floor -136 dbc/hz application as in figure 6. if output frequency range 30 60 mhz if output impedance 75 ? single-ended. see figure 8. if output return loss -20 db see figure 8, over operating range. all other spurs on if output 20 db v within channel bandwidth of 8mhz.
zl10100 data sheet 12 zarlink semiconductor inc. notes (1) when measuring from a 50 ? environment, the voltage step up transformation needs to be taken into account. (2) port powers up in high impedance state. (3) to maximize phase noise the tuning range should be minimised and q of resonator maximized. the application as in figure 6 ha s a tuning range of 200 mhz. (4) measured with 5 channels @ 77 dbuv centred on desired channel. synthesizer sda, scl input high voltage input low voltage input high current input low current leakage current hysterysis 3 0 -10 0.4 5.5 1.5 10 10 v v a a a v i2c ?fast mode? compliant input voltage = vcc input voltage = vee vcc = vee sda output voltage 0.4 0.6 v v isink = 3 ma isink = 6 ma scl clock rate 400 khz charge pump output current 3 10 na see table 6. vpin = 2 v charge pump drive output current 0.5 ma vpin = 0.7 v crystal frequency 2 20 mhz see figure 9 for application. recommended crystal series resistance 10 200 ? 4 mhz parallel resonant crystal external reference input frequency 2 20 mhz sinewave coupled through 10 nf blocking capacitor external reference drive level 0.2 0.5 vpp sinewave coupled through 10 nf blocking capacitor phase detector comparison frequency 4mhz equivalent phase noise at phase detector -152 -158 dbc/hz dbc/hz ssb, within loop bandwidth 2mhz 250 khz local oscillator programmable divider division ratio 240 32767 reference division ratio see table 1. output port sink current leakage current 2 10 ma a see note 2. vport = 0.7 vport = vcc address select input high current input low current 1 -0.5 ma ma see table 5 vin = vcc vin = vee electrical characteristics - test conditions (unless otherwise stated) t amb = -40 c to 85 c, vee = 0 v, vcc = 5 v5%. input frequency 1220 mhz. if output frequency 44 mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature a nd supply voltage unless otherwise stated. characteristic pin min. typ. max. units conditions
zl10100 data sheet 13 zarlink semiconductor inc. absolute maximum ratings - all voltages are referred to vee at 0 v. characteristic min. max. units conditions supply voltage -0.3 7 v rf input voltage 117 dbuv differential all i/o port dc offsets -0.3 vcc+0.3 v sda, scl dc offsets -0.3 6 v vcc = vee to 5.25 v storage temperature -55 150 c junction temperature 150 c package thermal resistance, chip to case 20 c/w package thermal resistance, chip to case 80 c/w power consumption at 5.25 v 700 mw esd protection 3.5 kv mil-std 883b method 3015 cat1
zl10100 data sheet 14 zarlink semiconductor inc. rf inputs reference oscillator oscillator inputs sda/scl (pins 12 and 11) if outputs output port figure 10 - input and output interface circuits rfinputb rfinput 5 6 xtal xtalcap 13 14 v cc 200 a lo lob 23 22 v ref 500 k 500 k v cc scl/sda 500 k ack * * on sda only v cc 75 ? 75 ? 28 1 if output if outputb po 17
zl10100 data sheet 15 zarlink semiconductor inc. loop amplifier add input figure 10 - input and output interface circuits v cc pump 220 16 15 drive v cc add 40 k 120 k 19
zl10100 data sheet 16 zarlink semiconductor inc. figure 11 - zl10100 evaluation board schematic

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